FIG. 1A shows a cross-sectional view of a MOS field effect transistor (FET) well known in the prior art. Such an MOS transistor typically includes source region 101s and drain region 101d, source extension region 102s and drain extension region 102d, channel 103, gate insulator 104, gate 105, and well 106, all of which are formed in semiconductor substrate 107. Additional doped layers may be present, but are not shown for simplicity. The source and drain regions 101s and 101d are heavily doped, typically with arsenic for n-type doping or boron for p-type doping. Doping levels are on the order of 1020 dopant atoms per cubic centimeter. The layers for regions 101s and 101d are typically 500–700 angstroms deep. The extension regions 102s and 102d are also heavily doped, with the same type of dopant atoms as the source and drain regions 101s and 101d, but the extension regions are shallower—typically 300 to 500 angstroms deep. FIG. 1B shows the doping profiles in the vertical directions (along the arrow A in FIG. 1A).
Extension regions 102s and 102d provide contacts to the channel region 103. The transistor operates by applying a bias to the gate 105 while grounding the well 106. For example, suppose the regions 101s, 102s, 102d and 101d are n-type, so that the majority carriers are electrons. If a positive voltage is placed on gate 105 with respect to the channel 103, no current will flow between the gate 105 and channel 103 because of the presence of thin gate insulator 104.
However, the positive voltage will attract electrons to the channel region 103, creating a thin layer of electrons (called an inversion layer) that connects source extension 102s to drain extension 102d, allowing current to flow between the source and drain. When the voltage on gate 105 is removed, the inversion layer in channel 103 ceases to exist, and the source is disconnected from the drain. In this manner, the transistor can be turned on and off.
In practice, the doping profiles for the various source and drain layers 101s, 101d, 102s and 102d are not perfectly abrupt (box-like). They are usually formed by diffusion processes that may involve several thermal cycles, causing the profiles to be somewhat rounded. For example, FIG. 1B shows two profiles 112A and 112B for the source extension 112s, following the arrow A in FIG. 1A. Line 112A shows a relatively abrupt profile and line 112B shows a less abrupt profile. Such variation in abruptness (between lines 112A and 112B) may be encountered in different semiconductor wafers under fabrication because each step in the fabrication process has a certain tolerance. Variation in individual process steps or the cumulative variation of a series of process steps can cause a loss of abruptness in the profile (e.g. may go from line 112A to line 112B). In addition, junction depth and peak doping concentration may vary depending on process properties, such as, for example, variation in annealing temperature. For example, profile 112B forms a deeper diffused profile than profile 112A, but at a smaller peak doping concentration.
The performance of the transistor is affected by the final doping profile after annealing. Profile depth, peak concentration, and profile abruptness are carefully controlled because they directly contribute to short-channel effects and speed of the transistor. A deeper and less abrupt profile in the vertical direction creates a higher off-state leakage current that leads to increased power consumption. A smaller peak doping concentration increases the resistance component between the source/drain region and the transistor channel, leading to a greater voltage drop between the source 101s and drain 101d (FIG. 1A).
This voltage drop reduces the ability of the transistor to drive the next stage, reducing the speed of the circuit.
A wide variety of methods are available in the prior art to characterize doped layers in semiconductors. However, such methods are unable (to the Applicants' knowledge) to provide this characterization in a small measurement size of less than 10 μm in diameter, and to do so without damage or contact to the layer being measured. These limitations require measurement on product wafers (as opposed to test or reference wafers) with doped areas formed in fine patterns, and effectively eliminate destructive methods such as Secondary Ion Mass Spectrometer (SIMS) and Scanning Capacitance Microscopy (SCM) from considerations.
Inference of doped layer properties is possible using electrical probing of transistors. However, this procedure requires physical contact of probes to a completed transistor structure. Moreover, this procedure is impractical in the middle of a process wherein the doped layers are being formed and the transistor is still incomplete. The time between performance of source/drain process steps and the first opportunity to electrically probe the completed structure can be days or weeks, greatly reducing the ability to implement real-time process control using electrical probing.
Borden et. al. have described methods for measurement of junction depth in U.S. Pat. Nos. 6,323,951 and 6,049,220. Moreover, U.S. Pat. Nos. 5,966,019 and 5,883,518 by Borden describe splitting of a laser beam into two parts of orthogonal polarization, and interference of reflection of the two orthogonal polarization components to form a signal indicative of semiconductor material properties. The just-described four patents are all incorporated by reference herein in their entirety as background.
Jiang et al. describe (in U.S. Pat. No. 6,556,306 which is incorporated by reference herein in its entirety as background) a method for determining the index of refraction of a thin film at a desired angular frequency. Jiang et al. disclose (in the abstract) generating an input desired-frequency pulse and an output detectable probe pulse. According to Jiang et al. a thin film is moved in and out of the path of the input pulse, creating an output pulse that alternates between a transmitted signal created when the film intercepts the input pulse path, and a reference signal, created when the sample is outside the input pulse path. The output pulse modulates the probe pulse, which is then detected with a photodetector and the difference between the transmitted signal and the reference signal is calculated. The above steps are repeated over a plurality of delay times between the input pulse and the probe pulse until a complete field waveform of the differential signal is characterized. The index of refraction is calculated by Jiang et al. as a function of a ratio between the differential signal for the thin film and the reference signal.
Heinrich et al. describe (in U.S. Pat. No. 4,758,092 which is incorporated by reference herein in its entirety as background) a method and means for optical detection of charge density modulation in a semiconductor. Heinrich et al. describe passing a polarized coherent light beam onto an interferometer which establishes two polarized beams. The two polarized beams are focused on a silicon device under test with one beam focused on or near an active device and one beam providing a reference. After passing through the device under test the two beams are reflected off a metal layer and back through the device under test where they are recombined by the beam splitter. However, the charge carriers affect the index of refraction of silicon, and by modulating the electrical charge in the active device a small modulation occurs in the index of refraction. The modulation affects the phase delay of the one beam near the active device in relation to the reference beam, and hence when the beams are recombined at the beam splitter they interfere and convert the relative phase modulation into an amplitude modulation which can be detected with a photodiode.
Heinrich et al. also state that the position of a single optical beam can be spatially modulated over a silicon wafer surface to detect stationary charge densities in one area relative to a reference area. The reference area may contain no charge density variation thereby giving an absolute reference value.